`timescale 1ms / 1ms
module Detector2test();
reg CP,Sin,nCR;
wire Out ;
  
// 实例化被测试模块
  Detector2 test (
    .Sin(Sin),
    .CP(CP),
    .nCR(nCR),
    .Out(Out)
  );   
initial 
  begin
    //Current_state=2'b00;
   // Next_state=2'b00;
    nCR=1'b0;
    CP=1'b0;
    #100 nCR = 1'b1;
    Sin=1'b0;
    #10Sin=1'b1;
    #10Sin=1'b0;
    #10Sin=1'b1;
    #10Sin=1'b0;
    #10Sin=1'b1;
    #10Sin=1'b0;
    #10Sin=1'b1;
    #10Sin=1'b0;
    #10Sin=1'b1;
    #10Sin=1'b0;
    #10Sin=1'b1;
    #10Sin=1'b0;
  end
always #5 CP = ~CP;
//always #10 Sin =~ Sin; 
  
   
  
   
 
 
endmodule
